1. Field of the Invention
The present invention relates to a serial transfer interface for correcting a loss generated at a high-frequency area.
2. Description of the Related Art
Recently, the PCI (peripheral component interconnect) and PCI-X used in a standard interface, etc., being utilized to connect the processor bus of a personal computer or a server to peripheral equipment, are going to be replaced with a PCI express which is a serial transfer interface in order to improve the data transfer speed.
Similarly, the ATA (AT attachment) used for connection of an HDD and CD-ROM to a storage device has been replaced with a serial ATA, and the SCSI (small computer system interface) has been replaced with a SAS (serial attached SCSI).
In these serial transfer interfaces, a method of obtaining a more stable signal waveform is requested to use a high-frequency band by automatically correcting a loss at each frequency band.
FIG. 1 shows an example of the configuration using a conventional serial transfer interface.
A serial transfer interface 70 shown in FIG. 1 is connected to a transmission path 72 for transmitting the signal waveform output from a transmitter 71, a circuit in a transmission path 72 (hereinafter referred to as a “subsequent circuit”). Generally, the transmission path 72 is constituted by a printed substrate, a connector, a cable, etc.
The serial transfer interface 70 includes: an equalizer unit 74 capable of externally selecting and setting a plurality of high pass filter characteristics; a latch unit 75 for amplifying a voltage so that a signal waveform adjusted by the equalizer unit 74 can be easily processed in a subsequent circuit, latching the signal waveform according to the synchronous clock generated by a clock generation unit 77, and outputting the signal waveform to the subsequent circuit; a digital filter unit 76 for controlling the clock generation unit 77 to appropriately follow a low frequency jitter including the difference in data transfer speed and suppress excess following to a high frequency jitter; and a clock generation unit 77 for generating a synchronous clock to latch a signal waveform at an appropriate point on a time axis.
The signal waveform output from the transmitter 71 is transmitted to the receiver 73 through the transmission path 72. The signal waveform input to the receiver 73 is adjusted by the equalizer unit 74, amplified by the latch unit 75, latched according to the synchronous clock, and output to the subsequent circuits.
The digital filter unit 76 detects a jitter from a signal waveform, instructs the clock generation unit 77 to appropriately follow a low frequency jitter, and instructs the clock generation unit 77 to suppress excessively following a high frequency jitter.
Then, the clock generation unit 77 generates a synchronous clock at an instruction from the digital filter unit 76, and provides it for the latch unit 75.
The waveform 1 shows the eye pattern measured between the transmitter 71 and the transmission path 72. Similarly, the waveform 2 shows the eye pattern between the transmission path 72 and the receiver 73. The waveform 3 shows the eye pattern between the equalizer unit 74 and the latch unit 75.
As shown by the waveform 2, the signal waveform has waveform variance by the characteristic variance by the change in environment (temperature change, etc.) of the transmission path 72, etc. and the characteristic of the LSI process.
The conventional serial transfer interface obtains the signal waveform (the waveform 2 shown in FIG. 1), etc. received by the receiver by an observation using an oscilloscope measurement device or a simulation, determines the optimum setting of the equalizer unit 74 while referring to the characteristic of the equalizer unit 74 of the receiver described on the datasheet, and manually performs the setting.
As explained above by referring to FIG. 1, according to the observation result by the oscilloscope of the signal waveform received by the receiver 73 and the characteristic of the equalizer unit 74 of the receiver 73 provided by the datasheet from an LSI maker, the substantially optimum setting of the equalizer unit 74 can be manually performed.
However, a long time is required to observe the signal waveform (for example, waveforms 1 through 3) of each path of the transmission path 72 and the receiver 73.
For example, since a four-lane path is provided for each of the forward and backward path, the waveform observation is required for a total of eight lanes. Additionally, to display an eye pattern on the oscilloscope, it requires a time to perform a setup for a measurement, and an observation time of about 20 seconds per lane.
Although a waveform can be measured and the equalizer unit 74 can be optimized using only representative lanes and the connection condition of other lanes can be matched with the representative lanes, it may be difficult for sufficient optimization. Furthermore, it is necessary to design a dedicated printed substrate.
Furthermore, the output terminal of the equalizer unit 74 is not assigned for observation of a waveform. Therefore, it may be difficult for some devices to observe a waveform due to deficient space for a probe. Therefore, it may not be possible to confirm that a signal waveform has been successfully corrected by the set equalizer.
Japanese Published Patent Application No.H11-203787 discloses an optical disk regeneration device provided with a characteristic control circuit of an equalizer unit for maintaining a predetermined or lower value of an error rate and a jitter value by providing the equalizer unit with a cutoff frequency characteristic control signal corresponding to the regeneration position of an optical disk, changing the gain characteristic of the equalizer unit, and correctly binarizing an RF signal.